Verilog and VHDL on Linux (Ubuntu)

by Mithrandir

For those interested in programming electronic components there is always the possibility to use Xilinx if you are on Windows. Of course, there is a Xilinx port for Linux but it is buggy application and a very large download. This article aims to give an alternative to this application. One that will need only a few KB of download from an apt-get source.

Of course, we are speaking about Icarus Verilog (iverilog), GHDL and GtkWave.

After installing each of them (command line, download, whatever), you can start desgning. Suppose we have the following source:

module bser(en, clk, in, out, done);
        input en, clk;
        input [7:0]in;
        output out, done;
        reg [2:0]cst;
        reg out, done;
 
        initial
        begin
                done = 0;
                cst = 3'b0;
                out = 0;
        end
 
        always @(posedge en)
        begin
                done = 0;
                cst = 3'b0;
                out = 0;
        end
 
        always @(posedge clk)
                if (en)
                begin
                        out = in[cst];
                        cst = cst + 1;
                        if (cst == 8)
                        begin
                                done = 1;
                                cst = 0;
                        end
                end
endmodule


We need to test our source manually, so we will write a benchmark file (consult the documentation for the syntax) in which we will introduce two lines for dumping information about variables:

module bser_tb;
        reg en, clk;
        reg [7:0]in;
        bser g(en, clk, in, out, done);
        initial
        begin
                en = 0; in=8'b00010111; clk=0;
                $dumpfile("bser_tb");
                $dumpvars;
                #10000 $finish;
        end
 
        always
        begin
                #1 clk = ~clk;
        end
 
        initial
        begin
                #2 en=1;
        end
endmodule


Now, we will compile the source, run it and then use gtkwave to see the results. All of this is very repetitive, so a Makefile was needed:


test_bser:
        iverilog bser.v bser_tb.v
        ./a.out
        gtkwave bser_tb
        rm -f a.out bser_tb


This is what we will obtain after a few milliseconds:

That’s all.