Code and Bugs

Coding things

Tag: Verilog

Writing a Compiler for Verilog – part 2

As previously stated, I am working on a Verilog Compiler in Python using PLY. The last article talked in a generic way about the project, from now on we will talk about specific parts of the compiler.

Today, we begain with the first part of any compiler: the lexing part.

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Writing a Compiler for Verilog – part 1

This year, I took a class named Numerical Computers II (I had Numerical Computers I last year). The course was about Computer Architecture and things like this. However, I ended up with a very fascinating homework: to write a compiler for Verilog in a team of 2 to 4 people. The deadline is coming soon (I have to finish it by Friday) but I need a break so I’ll post here my story.

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Formal Languages and Books

I’ve read two books in the last days. Both are related to Formal Languages, Automata Theory and Compilers. This will be another review article.

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VHDL Makefile

Here is a short example for the Makefile I’m currently using to compile and test my VHDL project:

.PHONY: all clean testbench
DEBUG = --vcd=$(VCDFILE) --stop-time=$(STOPTIME)
OBJS = clock.o
        make test
        ghdl --clean
        ghdl -m $(TARGET)
        ghdl -r $(TARGET) $(DEBUG)
        gtkwave $(VCDFILE)

Which is used in a terminal (providing you have gtkwave and ghdl installed) as follows:

$ make testbench TARGET=Chien_tb

Hoping to be useful, I’ll retire. I’ll be back in a few weeks with more details.

Verilog and VHDL on Linux (Ubuntu)

For those interested in programming electronic components there is always the possibility to use Xilinx if you are on Windows. Of course, there is a Xilinx port for Linux but it is buggy application and a very large download. This article aims to give an alternative to this application. One that will need only a few KB of download from an apt-get source.

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