Code and Bugs

Coding things

Tag: VHDL

VHDL Makefile

Here is a short example for the Makefile I’m currently using to compile and test my VHDL project:

.PHONY: all clean testbench
 
VCDFILE = tmp
STOPTIME = 42ns
DEBUG = --vcd=$(VCDFILE) --stop-time=$(STOPTIME)
CLEANUP = rm -f $(VCDFILE)
OBJS = clock.o
TARGET =
 
all:
        make test
 
clean:
        ghdl --clean
 
testbench:
        ghdl -m $(TARGET)
        ghdl -r $(TARGET) $(DEBUG)
        gtkwave $(VCDFILE)
        $(CLEANUP)

Which is used in a terminal (providing you have gtkwave and ghdl installed) as follows:

$ make testbench TARGET=Chien_tb

Hoping to be useful, I’ll retire. I’ll be back in a few weeks with more details.

Verilog and VHDL on Linux (Ubuntu)

For those interested in programming electronic components there is always the possibility to use Xilinx if you are on Windows. Of course, there is a Xilinx port for Linux but it is buggy application and a very large download. This article aims to give an alternative to this application. One that will need only a few KB of download from an apt-get source.

Read the rest of this entry »

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